A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

A device simulator that simulates device performance in the cyclic bias steady state was developed, and it was applied to GaAs hetero-junction FET (HJFET) pulse pattern effect. Although there is a large time-constant difference between the pulse signals and deep trap reactions, the simulator searches the cyclic bias steady states at about 30 iterations. A non-linear shift in the drain current level with the mark ratio was confirmed, which has been estimated from the rate equation of electron capture and emission based on Shockley-Read-Hall statistics for deep traps.

As wireless communication is penetrating every corner of the globe, the optimum design and accurate analysis of RF, power semiconductor devices become one of the biggest challenges in EDA and TCAD (Technology CAD) tool development. The performance gauge for these devices is quite different from that for either digital or analog devices aimed at small-signal applications in that the power gain, efficiency, and distortion (or the range of linearity) are the utmost design concerns. In this article, the methodology and mathematical foundation for numerical analysis of large signal distortion at the device simulation level are discussed. Although the harmonic balance (HB) method has long been used in circuit simulation for large signal distortion analysis, the implementation of the same method in device simulation faces daunting challenges, among which are the tremendous computational cost and memory storage management. But the benefits from conducting such a device level simulation are also obvious--for the first time, the impact of technology and structural variation of device on large signal performance can directly be assessed. The necessary steps to make the HB analysis feasible in device simulation are outlined and algorithmic improvement to ease the computation/storage burden is discussed. The applications of the device simulator for various RF power devices, including GaAs MESFETs and silicon LDMOS (lateral diffusion MOS) are presented, and the insight gained from such an analysis is provided.

Electro-thermal characteristics of the Si MOSFET in transient state are reported using a non-isothermal device simulator where both the transistor's self-heating and the thermal influence of its neighboring devices are duly taken into account. The thermal influence is estimated using a three-dimensional thermal simulator. Based on this set-up, we predict time-dependent electro-thermal characteristics of the Si MOSFET at gate switching and its drain breakdown conditions. We show that the time delay between the electrical response and the lattice temperature rise, is significant and thus can not be neglected. In addition, we found that avalanche and thermal breakdown characteristics largely depend on the slope of the drain input voltage.

A non-isothermal device simulation, consisting of solving heat flow equation three-dimensionally together with other semiconductor equations two-dimensionally, is reported for various arrangements of a pluralty of transistors mounted on a single chip. These arrangements are intended to simulate the real situation in an IC chip whereas a three-dimensional solution of the heat flow equation is aimed at accurately determining the thermal interdependence among individual transistors. As a result, the drain current versus drain voltage characteristics of a miniaturized transistor is found to exhibit a heat-induced negative resistance region.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

We have been studying on subthreshold characteristics of SOI (Silicon-On-Insulator) MOSFET's in terms of substrate bias dependence using a one-dimensional subthreshold device simulator based on Poisson equation in an SOI multilayer structure for estimating structural parameters of real devices. Here, we consider the quantum mechanical effects in the electron inversion layer of thin SOI MOSFET's, such as the two-dimensionally quantized electron states and transports, with a self-consistent solver of Poisson and Schrodinger equations and a mobility model by the relaxation time approximation. From results of simulations, we found a significant difference between this model and the classical model and concluded that the quantum mechanical effects need to be considered in analizing thin-film SOI devices.

We propose a nonlocal impact ionization model applicable for the drain region where electric field increases exponentially. It is expressed as a function of an electric field and a characteristic length which is determined by a thickness of gate oxide and a source/drain junction depth. An analytical substrate current model for n-MOSFET is also derived from the new nonlocal impact ionization model. The model well explains the reason why the theoretical characteristic length differs from empirical expressions used in a pseudo two-dimensional model for MOSFET's. The nonlocal impact ionization model implemented in a device simulator demonstrates that the new model can predict substrate current correctly in the framework of drift-diffusion model.

Carrier mobility is one of the most fundamental parameters in semiconductor device modeling, and many mobility models have already been reported. Especially for numerical device simulators, many local models which are functions of impurity concentration and electric field at each local point have been studied. However, concerning their dependence on impurity concentration including carrier screening effects, these models suffer parameter fitting procedure because of their empirical formulation. In such models, carrier screening effects to the Coulomb potential of ionized impurity are not sufficiently considered, although we can find some models which treat the effects as only a small perturbation term. According to the simple theory of Brooks and Herring, carrier screening effects should be included in strong combination with impurity concentration terms and cannot be treated as additional perturbations. Although Brooks-Herring theory is successful, it also suffers from overestimation of the mobility values at concentration higher than 1018 cm-3 which causes some other complicated phenomena. Therefore there have been no models which directly use Brooks-Herring formula. But it is true that such screening effects should be considered when carrier concentration differs from impurity concentration as in the inversion layers of MOSFETs. We have developed a new mobility model for its dependence of impurity and carrier concentration based on the theory of Brooks-Herring. Brooks-Herring theory is based on simple physics of screened Coulomb potential, and therefore makes the model to include effects of free carriers without an artifitial formula. For high doping regime, an additional term has been introduced in Brooks-Herring formula to correct the high doping effects. Except for this term, the model should be most appropriate for including the carrier screening effects upto the concentration of 1018 cm-3. The new model is implimented in a device simulator, and is applied to the evaluation of MOSFETs especially for the universal curves of inversion layer mobility. Moreoever, the applications to the depletion-type MOSFET confirm the validity of the screening effects. The purpose of this paper is to propose the new mobility model and to show its validity through these applications to MOSFETs.

The ultimate minimum energy of switching mechanism for MOS integrated circuits have been studied. This report elucidates the evaluation methods for minimum switching energy of instantaneous discharged mechanism after charging one, namely, recycled energy of the MOS device. Two approaches are implemented to capture this concept. One is a switching energy by the time-dependent gate capacitance (TDGC) model ; the other one by results developed by transient device simulation, which was implemented using Finite Element Method (FEM). It is understood that the non-recycled minimum swhiching energies by both approaches show a good agreement. The recycled energies are then calculated at various sub-micron gate MOS/SOI devices and can be ultra-low power of the MOS integrated circuits, which may be possible to build recycled power circuitry for super energy-saving in the future new MOS LSI. From those results, (1) the TDGC is simultaneously verified by consistent match of the non-recycled minimum switching energies; (2) the recycled switching energy is found to be the ultimate lower bound of power for MOS device; (3) the recycled switching energy can be saved up to around 80% of that of current MOS LSI.

In this paper, the formulation of unified transport model is reviewed along with its implementation in a three-dimensional device simulator. The model features an accurate description of the energy exchange among electrons, holes and lattice, and is therefore suitable for self-consistently simulating thermal effects and non-stationary phenomena, as well as their possible interactions. Despite the model complexity, it is shown that the computational effort required for its solution is reasonably close to more conventional approaches. Application examples are also given, in which both unipolar and bipolar devices are simulated, discussing the relative importance of different phenomena and highlighting the simultaneous occurrence of carrier and lattice heating.

In order to achieve an efficient and reliable prediction of device performance by numerical device simulation, a discretization mesh must be generated with an adequate, but not redundant, density of mesh points. However, manual mesh optimization requires user's trial and error. This task annoys the user considerably, especially when the device operation is not well known, or the required mesh-point density strongly depends on the bias condition, or else the manipulation of the mesh is difficult as is expected in 3D. Since these situations often happen in designing advanced VLSI devices, it is highly desirable to automatically optimize the mesh. Adaptive meshing techniques realize automatic optimization by refining the mesh according to the discretization error estimated from the solution. The performance of mesh optimization depends on a posteriori error indicators adopted to evaluate the discretization error. In particular, to obtain a precise terminal-current value, a reliable error indicator for the current continuity equation is necessary. In this paper, adaptive meshing based on the current continuity equation is investigated. A heuristic error indicator is proposed, and a methodology to extend a theoretical error indicator proposed for the finite element method to the requirements of device simulation is presented. The theoretical indicator is based on the energy norm of the flux-density error and is applicable to both Poisson and current continuity equations regardless of the mesh-element shape. These error indicators have been incorporated into the adaptive-mesh device-simulator HFIELDS, and their practicality is examined by MOSFET simulation. Both indicators can produce a mesh with sufficient node density in the channel region, and precise drain current values are obtained on the optimized meshes. The theoretical indicator is superior because it provides a better optimization performance, and is applicable to general mesh elements.

A software package has been developed for simulating complex silicon and heterostructure devices in 3D. Device geometries are input with a mouse-driven geometric modeler, thus simplifying the definition of complex 3D shapes. Single components of the device are assembled through boolean operations. Tetrahedra are used for grid generation, since any plane-faced geometry can be tessellated with tetrahedra, and point densities can be adapted locally. The use of a novel octree-like data structure leads to oriented grids where desirable. Bad angles that prevent the convergence of the control volume integration scheme are eliminated mostly through topological transformations, thus avoiding the insertion of many redundant grid points. The discretized drift-diffusion equations are solved with an iterative method, using either a decoupled (or Gummel) scheme, or a fully coupled Newton scheme. Alternatively, generated grids can be submitted to a Laplace solver in order to calculate wire capacitances and resistances. Several examples of results illustrate the flexibility and effectiveness of this approach.

We studied minority carrier collection in high-density stacked-capacitor DRAM cells using a three-dimensional device simulator. We estimated the collected charge for incident angle, location, and junction size and showed that, compared to the conventional structure by a twin-well process, an n-well-guarded cell array fabricated using a triple-well process effectively reduced the charge injected into cells. The reduction was because the n-well absorbed most of the electrons. A so-called "size-effect" did exist and smaller junctions performed better. We concluded that storage capacitance in a 256 M-bit DRAM cell could be reduced, compared to that in previous devices, which would, in turn, help reduce costs in fabricating high-density DRAM.

Thin- and ultra-thin-film SOI MOSFET's are promising candidates to overcome the constraints for future miniaturized devices. This paper presents simulation results for a 0.1 µm gate length SOI MOSFET structure using a two-dimensional/two-carrier device simulator with a nonlocal model for the avalanche induced carrier generation. For the suppression of punchthrough effect in devices with a channel doping of 1 1016 cm-3 and 5 nm thick gate oxide it is found that the SOI layer thickness has to be reduced to at least 20 nm. The thickness of the buried oxide should not be smaller than 50 nm in order to avoid the degradation of thin SOI performance advantages. Investigating ways to suppress the degradation of the sub-threshold slope factor at these device dimensions it was found in contrast to the common expectation that the S-factor can be improved by increasing the body doping concentration. This phenomenon, which is a unique feature of thin-film depleted SOI MOSFET's, is explained by an analytical mode. At lower doping the area of the current flow is reduced by a decreasing effective channel thickness resulting in a slope factor degradation. Other approaches for S-factor improvement are the reduction of the channel edge capacitances by source/drain engineering or the decrease of SOI thickness or gate oxide thickness. For the latter approach a higher permittivity gate insulating material should be used in order to prevent tunnelling. The low breakdown voltage can be increased by utilizing an LDD structure to be suitable for a 1.5 V power supply. However, this is at the expense of reduced current drive. An alternative could be the supply voltage reduction to 1.0 V for single drain structure use. A dual-gated SOI MOSFET has an improved performance due to the parallel combination of two MOSFET's in this device. A slightly reduced breakdown voltage indicates a larger drain electric field present in this structure.

For the development of a practical device simulation, it is necessary to solve the large sparse linear equations with a high speed computation of direct solution method. The use of parallel computation methods to solve the linear equations can reduce the CPU time greatly. The Multi Step Diakoptics (MSD) algorithm, is proposed as one of these parallel computation methods with direct solution, which is based on Diakoptics, that is, a tearing-based parallel computation method for sparse linear equations. We have applied the MSD algorithm to device simulation. This letter describes the partition and connection schedules in the MSD algorithm. The evaluation of this algorithm is done using a massively parallel computer with distributed memory (AP1000).

In this paper, a "hydrodynamic" version of the three-dimensional code HFIELDS-3D is used to achieve a detailed knowledge on the distribution of the substrate current inside a recessed-oxide MOSFET. The physical model features a temperature-dependent formulation of the impact-ionization rate, allowing non-local effects to be accounted for. The discretization strategy relies on the Box Integration scheme and uses suitable generalizations of the Scharfetter-Gummel technique for the energy-balance equation. The simulation results show that the narrow-channel effect has a different impact on drain and substrate currents. Further three-dimensional effects, such as the extra heating of the carriers at the channel edge, are demonstrated.

We have developed an efficient general-purpose two-dimensional device simulation system which consists of a solver, and pre- and post-processors. This system can easily handle any complicated device having a non-rectangular shape. It can also be applied to compound semiconductor devices with heterojunctions, including optical devices such as laser diodes. In order to handle any device, a new program for construction of device geometry is developed as a preprocessor. It has an efficient graphic interface to reduce the time required to input data for simulations, which is a very time consuming task for complicated devices. A new efficient data structure representing device geometry is introduced in the program. During postprocessing, any physical quantity can be displayed on the multi-window screen. In addition, a general-purpose solver for basic semiconductor equations is implemented in the system. Using this system, any device can be successfully analyzed in a unified manner and the turn-around time for the simulation is significantly reduced.

We present a new apparent bandgap narrowing model for semiconductor device simulation. The new model is derived from revised data of previous measurements on the apparent bandgap narrowing by using a corrected intrinsic carrier concentration. The revised values reveal sufficient agreement with our theoretical calculation. The new model is implemented in a triangular mesh device simulator TRIMEDES. Simulated BJT current-voltage and current-temperature characteristics using the proposed model reveal excellent agreement with measurements.